A programmable logic device, such as field programmable gate array (FPGA) or a complex programmable logic device (CPLD), may be used in a variety of applications. A programmable logic device (PLD) offers the advantage of being reprogrammable in the field (e.g., while on the circuit board in its operational environment).
A drawback of a conventional PLD is that, while being programmed (which may take seconds to load an external configuration bitstream), the PLD enters a sleep state, with its input and output pins typically disabled (e.g., non-responsive to input signals while providing indeterminate output signals). If the PLD is in a critical path or is used to control critical functions, these drawbacks may be unacceptable. Furthermore, glitches on the output signals provided by the PLD during programming or after reconfiguration generally would be unacceptable while the PLD is controlling critical functions. As a result, there is a need for improved programming and configuration techniques for PLDs.